View MC33470-D_3017750.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

synchronous rectification dc/dc converter programmable integrated controller the mc33470 is a digitally programmable switching voltage regulator, specifically designed for microprocessor supply, voltage regulator module and general purpose applications, to provide a high power regulated output v oltage using a minimum of external parts. a 5bit digitaltoanalog converter defines the dc output voltage. this product has three additional features. the first is a pair of high speed comparators which monitor the output voltage and expedite the circuit response to load current changes. the second feature is a soft start circuit which establishes a controlled response when input power is applied and when recovering from external circuit fault conditions. the third feature is two output drivers which provide synchronous rectification for optimum efficiency. this product is ideally suited for computer, consumer, and industrial equipment where accuracy, efficiency and optimum regulation performance is desirable. mc33470 features: ? 5bit digitaltoanalog converter allows digital control of output voltage ? high speed response to transient load conditions ? output enable pin provides on/off control ? programmable soft start control ? high current output drives for synchronous rectification ? internally trimmed reference with low temperature coefficient ? programmable overcurrent protection ? overvoltage fault indication ? functionally similar to the ltc1553 on semiconductor ? semiconductor components industries, llc, 2001 august, 2001 rev. 2 1 publication order number: mc33470/d mc33470 dw suffix plastic package case 751d (so20l) 20 1 device operating temperature range package ordering information mc33470dw so20l t a = 0 to +75 c synchronous rectification dc/dc converter programmable integrated controller semiconductor technical data pin connections 13 7 4 3 a gnd ot fault p wrgd vid4 vid3 vid2 vid1 vid0 11 12 14 15 16 17 18 10 9 8 6 5 (top view) compensation ss i fb i max sense v cc p gnd 1 g2 outen g1 19 20 2 p v cc
mc33470 http://onsemi.com 2 oscillator pwm comparator ota error amp v cc sense compensation p gnd g1 g2 i fb over current detect outen power good vid0 vid1 vid2 vid3 v ref v cc voltage identification code input digitally programmed reference v cc v ref r s q pwm latch + 0.96 v ref 1.04 v ref 5 vid4 18 17 16 15 14 410 9 14 3 1 8 20 2 19 0.93 v ref 1.04 v ref 13 a gnd 6 ss 800 m over temp 11 i max 7 10 m a 2.5 v 1.5 v en 90 m a 190 m a s r q delay fault 1.14 v ref 20 m a ot q + + + delay simplified block diagram p v cc maximum ratings (t c = 25 c, unless otherwise noted.) rating symbol value unit power supply voltage v cc 7.0 v output driver supply voltage (operating) p v cc 18 v i max , i fb inputs v in 0.3 to 18 v all other inputs and digital v in 0.3 to v (ot , fault , power good) outputs v cc + 0.3 power dissipation and thermal characteristics maximum power dissipation case 751d dw suffix (t a = 70 c) p d 0.60 w thermal resistance junctiontoambient r q ja 91 c/w thermal resistance junctiontocase r q jc 60 c/w operating junction temperature t j 125 c operating ambient temperature (notes 1 and 2) t a 0 to +70 c storage temperature range t stg 55 to +125 c note: esd data available upon request
mc33470 http://onsemi.com 3 electrical characteristics (v cc = 5.0 v, p vcc , = 12 v for typical values t a = low to high [notes 1, 2, 3], for min/max values t a is the operating ambient temperature range that applies, unless otherwise noted.) characteristic symbol min typ max unit oscillator frequency (v cc = 4.5 to 5.5 v) f osc 210 300 390 khz feedback amplifier voltage feedback input threshold (note 4) v sense 1.764 1.8 1.836 v vid0, vid1, vid2 and vid4 = a1o and vid3 = a0o 2.744 2.8 2.856 v vid4 = a1o and vid0, vid1, vid2 and vid3 = a0o 3.43 3.5 3.57 v input bias current (v cm = 2.8 v) i ib 20 m a transconductance (v cm = 2.8 v, v comp = 2.0 v) g m 400 800 1200 m mho open loop voltage gain (v comp = 2.0 v) a vol 67 db output line regulation (v cc = 4.5 to 5.5 v) reg line 7.0 mv output load regulation reg load 5.0 mv output current m a source i oh 120 sink i ol 120 pwm section duty cycle at g1 output % maximum dc max 77 88 95 minimum dc min 0 propagation delay m s comp input to g1 output, t j = 25 c t plh1 0.1 comp input to g2 output, t j = 25 c t plh2 0.1 softstart section charge current (v softstart = 0 v) i chg 7.0 10 13 m a discharge current under current limit (note 5) i ssil 30 90 150 m a (v softstart = 2.0 v, v sense = v out , v imax = v cc , v ifb = 0 v) discharge current under hard current limit i sshil 40 64 ma (v softstart = 2.0 v, v sense < v out /2, v imax = v cc , v ifb = 0 v) hard current limit hold time t sshil 100 200 300 m s imax input sink current (v in max = v cc , v ifb = v cc ) i ol 133 190 247 m a power good output threshold for logic a1o to a0o transition v th v sense upper threshold 1.04 1.07 lower threshold 0.93 0.96 response time t rpg m s logic a0o to a1o (v sense changes from 0 v to v o ) 200 400 600 logic a1o to a0o (v sense changes from v o to 0 v) 50 100 150 sink current (v ol = 0.5 v) i olpg 10 ma output low voltage (i ol = 100 m a) (note 6) v olpg 250 500 mv notes: 1. maximum package power dissipation limits must be observed. 2. low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. 3. vid1, vid3, vid4 = logic 0, and vid0, vid2 = logic 1. 4. v sense is provided from a low impedance voltage source or shorted to the output voltage. 5. under a typical soft current limit, the net softstart discharge current will be 90 m a (i ssil ) 10 m a (i chg ) = 80 m a. the softstart sink to source current ratio is designed to be 9:1. 6 sense (pin 6) = 5.0 v, comp (pin 10) open, vid4, vid2, vid1, vid0 = 1.0, vid3 = 0. 7. outen is internally pulled low if vid0, 1, 2, 3, and 4 are floating. 8. due to internal pullup resistors, there will be an additional 0.5 ma per pin if any of the vid0, 1, 2, 3, or 4 pins are pull ed low. p v cc
mc33470 http://onsemi.com 4 electrical characteristics (continued) (v cc = 5.0 v, p vcc , = 12 v for typical values t a = low to high [notes 1, 2, 3], for min/max values t a is the operating ambient temperature range that applies, unless otherwise noted.) characteristic unit max typ min symbol fault output threshold for logic a0o to a1o transition v thf 1.12 1.14 1.2 v ref v sense response time switches from 2.8 v to v cc t rf 50 100 150 m s sink current (v ol = 0.5 v) i olf 10 ma overtemperature output threshold for logic a1o to a0o transition (outen voltage decreasing) v thouten 1.85 2.0 2.2 v delay time t dot 25 50 100 m s sink current (v ol = 0.5 v) i olf 10 ma logic inputs (vid0, vid1, vid2, vid3, vid4) input low state v il 0.8 v input high state v ih 3.5 v input impedance r in 10 k w output enable control (outen) overtemperature driver disable and reset v otdd 1.55 1.70 1.85 v (outen voltage decreasing) (note 7) output sections (g1, g2) source resistance (v sense = 2.0 v, v g = p vcc 1.0 v) p v cc r oh 0.5 w sink resistance (v sense = 0 v, v g = 1.0 v) r ol 0.5 output voltage with outen reset (i sink = 1.0 ma) v ol 0.1 0.5 v output voltage rise time (c l = 10 nf, t j = 25 c) t r 70 140 ns output voltage fall time (c l = 10 nf, t j = 25 c) t f 70 140 ns g1, g2 nonoverlap time (c l = 10 nf, t j = 25 c) t nol 30 150 210 ns total device minimum operating voltage after turnon ( p vcc decreasing) p v cc p v cc min 10.8 v minimum operating voltage after turnon (v cc decreasing) v cc min 3.0 4.25 v v cc current (note 8) (outen and p vcc open, p v cc i cc 3.7 8.0 ma vid0, 1, 2, 3, 4 floating) p vcc current (outen = 5.0 v, vid0, 1, 2, 3, 4 open, p vcc = 12 v) p v cc p v cc p i cc 15 ma notes: 1. maximum package power dissipation limits must be observed. 2. low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. 3. vid1, vid3, vid4 = logic 0, and vid0, vid2 = logic 1. 4. v sense is provided from a low impedance voltage source or shorted to the output voltage. 5. under a typical soft current limit, the net softstart discharge current will be 90 m a (i ssil ) 10 m a (i chg ) = 80 m a. the softstart sink to source current ratio is designed to be 9:1. 6 sense (pin 6) = 5.0 v, comp (pin 10) open, vid4, vid2, vid1, vid0 = 1.0, vid3 = 0. 7. outen is internally pulled low if vid0, 1, 2, 3, and 4 are floating. 8. due to internal pullup resistors, there will be an additional 0.5 ma per pin if any of the vid0, 1, 2, 3, or 4 pins are pull ed low. p v cc
mc33470 http://onsemi.com 5 figure 1. output drive waveform figure 2. 5.0 v supply current figure 3. error amplifier transient response figure 4. drive output source/sink saturation voltage versus load current figure 5. feedback circuit load transient response figure 6. feedback loop gain and phase versus frequency 2.5 ms/div v o = 2.8 v i o transient = 0.3 to 16 a figure 13 circuit 200 ns/div v o = 2.8 v i o = 3.3 a figure 13 circuit 0 v o = 2.8 v i o transient = 0.3 to 16 a figure 13 circuit 2.5 ms/div 2.0 v/div 500 mv/div 50 mv/div input voltage (v) 0 1.0 2.0 3.0 5.0 8.0 8.0 7.0 6.0 4.0 0 1.0 2.0 3.0 4.0 5.0 6.0 t a = 25 c 7.0 0 -0.5 -1.0 0 0.5 1.0 0 0.2 0.4 0.6 0.8 1.0 1.2 source saturation (load to ground) ground f, frequency (hz) 300 -10 -5.0 0 5.0 20 10 15 1.0 k 10 k 100 k 300 k 3.0 k 30 k 180 150 120 90 0 60 30 phase v ccp = 12 v v cc = 5.0 v v o = 2.8 v i o = 3.3 a t a = 25 c gain i cc , supply current (ma) sink saturation loop gain (db) p v cc p v cc 12v p v cc open (loadtop v cc )
mc33470 http://onsemi.com 6 figure 7. drive output source/sink saturation voltage versus load current figure 8. feedback threshold voltage versus temperature figure 9. i max current versus temperature figure 10. v sense current source versus temperature figure 11. v cc undervoltage lockout trip point versus temperature figure 12. oscillator frequency versus temperature -4.0 -3.5 -3.0 -2.0 -1.0 -0.5 -2.5 -1.5 0 0.5 1.0 -4.0 -2.0 2.0 4.0 0 -6.0 -1.5 -1.0 -0.5 0.5 1.5 2.0 0 1.0 2.5 -2.0 -2.5 -5.0 -4.0 -2.0 2.0 4.0 5.0 0 -0.2 0.8 -50 -25 0 25 50 75 t a , ambient temperature ( c) i o = 3.3 a v o = 2.8 v 100 12 5 0.2 0.4 0.6 0 1.0 frequency (khz) 10 100 1000 1.0 10 100 1000 180 150 120 90 0 60 30 phase v ccp = 12 v v cc = 5.0 v v o = 2.8 v r2 = 18.2 k c16 = 0 t a = 25 c figure 13 gain gain ( mho) m ? , excess phase (degrees) -75 threshold voltage change (%) -50 -25 0 25 50 75 t a , ambient temperature ( c) 100 125 -75 i o = 3.3 a v o = 2.8 v i max , current change (%) -50 -25 0 25 50 75 t a , ambient temperature ( c) 100 12 5 -75 i o = 3.3 a v o = 2.8 v i sense , current change (%) -50 -25 0 25 50 75 t a , ambient temperature ( c) 100 125 -75 v cc increasing i o = 3.3 a v o = 2.8 v uvlo threshold change (%) -50 -25 0 25 50 75 t a , ambient temperature ( c) 100 12 5 -75 i o = 3.3 a v o = 2.8 v uvlo threshold change (%)
mc33470 http://onsemi.com 7 figure 13. mc33470 application circuit outen j1-b5 up# d1 j1-b6 input voltage v in = 5.0 v j1-a1, a2, a3, b1, b2 l2 1.5 h m ot 11 19 outen r10 10 5 v cc c3 4.7 f m r1 2.7 k c5 470 pf c1 150 16 v f m c2 150 16 v f m ++ q2 mmsf3300r2 5, 6, 7, 8 l1 1.5 m h v o 0.3 to 14 a j1-a10, a12, a14, a16, a18, a20, b11, b13, b15, b17, b19 c10 820 4.0 v f m c11 820 4.0 v f m c13 1.0 f m v ss j1-a11, a13, a15 a17, a19, b10, b12 b14, b16, b18, b20 4 2, 3 5, 6, 7, 8 d2 mbrd1035ct q4 mmsf3300r2 q3 mmsf3300r2 r7 4.7 v drive g1 g2 r9 10 4 2, 3 5, 6, 7, 8 p 2 r8 4.7 fault indicate r6 100 k r5 1.2 k fault 20 8 1 3 12 r4 56 u1 r q delay 1.14 v ref compensation 10 c16 2200 pf r2 8.2 k c17 100 pf a 4 power good 13 20 a m s r q s delay 1.04 v ref 0.96 v ref 1.04 v ref 0.96 v ref + + + + pwm latch 90 a m en over current detect 190 a m 4.0/3.8 undervoltage lockout v ref pwm comparator 1.5 v 2.5 v ota error amp 800 m 64 ma + sense 6 ss 9 r3 100 k to p j1-b9 m c18 0.01 f m v ref over temp digitally programmed reference oscillator 10 a m v cc v ref /2 vid0 18 j1-a7 vid1 vid2 vid3 vid4 17 16 15 14 j1-b7 j1-a8 j1-b8 j1-a9 12 v j1-a4, b4 voltage identification code input i fb i max 7 c6 1.0 f m + v cc c1, c2 oscon 16sa150m c3 tdk c3216y5v1c476z c6, c13 tdk c3216y5v1c106z c10, c11 oscon 4sp820m j1 amp 5329567 l1, l2 coilraft u6904 gnd gnd q1 mmsf3300r2
mc33470 http://onsemi.com 8 figure 14. timing diagram 12 v 5.0 v uvl threshold uvl threshold internal v ref timing capacitor compensation g1 g2 1.5 v 2.5 v operating description the mc33470 is a monolithic, fixed frequency power switching regulator specifically designed for dctodc converter applications which provide a precise supply voltage for state of the art processors. the mc33470 operates as fixed frequency, voltage mode regulator containing all the active functions required to directly implement digitally programmable stepdown synchronous rectification with a minimum number of external components. oscillator the oscillator frequency is internally programmed to 300 khz. the charge to discharge ratio is controlled to yield a 95% maximum duty cycle at the switch outputs. during the fall time of the internal sawtooth waveform, the oscillator generates an internal blanking pulse that disables the g1 output switching mosfet. the internal sawtooth waveform has a nominal peak voltage of 2.5 v and a valley voltage of 1.5 v. pulse width modulator the pulse width modulator consists of a comparator with the oscillator ramp voltage applied to the noninverting input, while the error amplifier output is applied to the inverting input. output switch conduction is initiated when the ramp waveform is discharged to the valley voltage. as the ramp voltage increases to a voltage that exceeds the error amplifier output, the latch resets, terminating output g1 mosfet conduction, and turning on output g2 mosfet, for the duration of the oscillator ramp. this pwm/latch combination prevents multiple output pulses during a given oscillator cycle. the sense voltage input at pin 6 is applied to the noninverting inputs of a pair of high speed comparators. the high speed comparators' inverting inputs are tied 0.96 x v ref and 1.04 x v ref , respectively, to provide an optimum response to load changes. when load transients which cause the output voltage to fall outside a 4% regulation window occur, the high speed comparators override the pwm comparator to force a zero or maximum duty cycle operating condition until the output voltage is once again within the linear window. when voltages are initially provided to the supply pins, v cc and p v cc , undervoltage lockout circuits monitor each of the supply voltage levels. both g1 and g2 output pins are held low until the v cc pin voltage exceeds 4.0 v and the p v cc pin voltage exceeds 9.0 v. error amplifier and voltage reference the error amplifier is a transconductance type amplifier, having a nominal transconductance of 800 m mho. the transconductance has a negative temperature coefficient. typical transconductance is 868 m mho at 0 c and 620 m mho at 125 c junction temperature. the amplifier has a cascode output stage which provides a typical 3.0 megaohms of
mc33470 http://onsemi.com 9 impedance. the typical error amplifier dc voltage gain is 67 db. external loop compensation is required for converter stability. compensation components may be connected from the compensation pin to ground. the error amplifier input is tied to the sense pin which also has an internal 20 m a current source to ground. the current source is intended to provide a 24 mv offset when an external 1.2 k resistor is placed between the output voltage and the sense pin. the 24 mv offset voltage is intended to allow a greater dynamic load regulation range within a given specified tolerance for the output voltage. the offset may be increased by increasing the resistor value. the offset can be eliminated by connecting the sense pin directly to the regulated output voltage. the voltage reference consists of an internal, low temperature coefficient, reference circuit with an added offset voltage. the offset voltage level is the output of the digitaltoanalog converter. control bits vid0 through vid4 control the amount of offset voltage which sets the value of the voltage reference, as shown in table 1. the vid04 input bits each have internal 10 k pullup resistances. therefore, the reference voltage, and the output voltage, may be programmed by connecting the vid pins to ground for logic a0o or by an open for a logic a1o. t ypically, a logic a1o will be recognized by a voltage > 0.67 x v cc . a logic a0o is a voltage < v cc /3. mosfet switch outputs the output mosfets are designed to switch a maximum of 18 v, with a peak drain current of 2.0 a. both g1 and g2 output drives are designed to switch nchannel mosfets. output drive controls to g1 and g2 are phased to prevent cross conduction of the internal ic output stages. output dead time is typically 100 nanoseconds between g1 and g2 in order to minimize cross conduction of the external switching mosfets. current limit and softstart controls the softstart circuit is used both for initial power application and during current limit operation. a single external capacitor and an internal 10 m a current source control the rate of voltage increase at the error amplifier output, establishing the circuit turn on time. the g1 output will increase from zero duty cycle as the voltage across the softstart capacitor increases beyond about 0.5 v. when the softstart capacitor voltage has reached about 1.5 v, normal duty cycle operation of g1 will be allowed. an overcurrent condition is detected by the current limit amplifier. the current limit amplifier is activated whenever the g1 output is high. the current limit amplifier compares the voltage drop across the external mosfet driven by g1, as measured at the i fb pin, with the voltage at the i max pin. because the i max pin draws 190 m a of input current, the overcurrent threshold is programmed by an external resistor. referring to figure 13, the current limit resistor value can be determined from the following equation: r1 [( i l(max) )(r ds(on) )] (i max ) where: i l(max) i o i ripple 2 = maximum load current = inductor peak to peak ripple current i o i ripple outen input and ot output pins on and off control of the mc33470 may be implemented with the outen pin. a logic a1o applied the outen pin, where a logic a1o is above 2.0 v, will allow normal operation of the mc33470. the outen pin also has multiple thresholds to provide over temperature protection. an negative temperature coefficient thermistor can be connected to the outen pin, as shown in figure 15. together with r s , a voltage divider is formed. the divider voltage will decrease as the thermistor temperature increases. therefore, the thermistor should be mounted to the hottest part on the circuit board. when the outen voltage drops below 2.0 v typically, the mc33470 ot pin open collector output will switch from a logic a1o to a logic a0o, providing a warning to the system. if the outen voltage drops below 1.7 v, both g1 and g2 output driver pins are latched to a logic a0o state. figure 15. outen/ot overtemperature function v cc r s ntc thermistor mc33470 outen ot 10 k v cc
mc33470 http://onsemi.com 10 applications information design example given the following requirements, design a switching dctodc converter: = 5.0 v = 12 v = 10111 output voltage = 2.8 v = 0.3 a to 14 a v cc v ccp vid40 bits output current efficiency > 80% at full load output ripple voltage 1% of output voltage 1. choose power mosfets. in order to meet the efficiency requirement, mosfets should be chosen which have a low value of r ds(on) . however, the threshold voltage rating of the mosfet must also be greater than 1.5 v, to prevent turn on of the synchronous rectifier mosfets due to dv/dt coupling through the miller capacitance of the mosfet draintosource junction. figure 16 shows the gate voltage transient due to this effect. in this design, choose two parallel mmsf3300 mosfets for both the main switch and the synchronous rectifier to maximize efficiency. 2. d v o /v in = 2.8/5.0 = 0.56 3. inductor selection in order to maintain continuous mode operation at 10% of full load current, the minimum value of the inductor will be: l min = (v in v o )(dts)/(2i o min ) = (5 2.8)(0.56 x 3.3 m s)/(2 x 1.4 a) = 1.45 m h coilcraft's u6904, or an equivalent, provides a surface mount 1.5 m h choke which is rated for for full load current. 4. output capacitor selection v ripple d i l x esr, where esr is the equivalent series resistance of the output capacitance. therefore: esr max = v ripple / d i l = 0.01 x 2.8 v/1.4 a = 0.02 w maximum the avx tps series of tantalum chip capacitors may be chosen. or oscon capacitors may be used if leaded parts are acceptable. in this case, the output capacitance consists of two parallel 820 m f, 4.0 v capacitors. each capacitor has a maximum specified esr of 0.012 w . 5. input filter as with all buck converters, input current is drawn in pulses. in this case, the current pulses may be 14 a peak. if a 1.5 m h choke is used, two parallel oscon 150 m f, 16 v capacitors will provide a filter cutoff frequency of 7.5 khz. 6. feedback loop compensation the corner frequency of the output filter with l = 1.5 m h and c o = 1640 m f is 3.2 khz. in addition, the esr of each output capacitor creates a zero at: f z = 1/(2 p c esr) = 1/(2 p x 820 m f x 0.012) = 16.2 khz the dc gain of the pwm is: gain = v in /v pp = 5/1 = 5.0. where v pp is the peaktopeak sawtooth voltage across the internal timing capacitor. in order to make the feedback loop as responsive as possible to load changes, choose the unity gain frequency to be 10% of the switching frequency, or 30 khz. plotting the pwm gain over frequency, at a frequency of 30 khz the gain is about 16.5 db = 0.15. therefore, to have a 30 khz unity gain loop, the error amplifier gain at 30 khz should be 1/0.15 = 6.7. choose a design phase margin for the loop of 60 . also, choose the error amp type to be an integrator for best dc regulation performance. the phase boost needed by the error amplifier is then 60 for the desired phase margin. then, the following calculations can be made: k = tan [boost/2 + 45 ] = tan [60/2 + 45] = 3.73 error amp zero freq = f c /k = 30 khz/3.73 = 8.0 khz error amp pole freq = k fc = 3.73 x 30 khz = 112 khz r2 = error amp gain/g m = 6.7/800 m = 8.375 k use an 8.2 k standard value c16 = 1/(2 p r2 f z ) = 1/(2 p x 8.2 k x 8.0 khz) = 2426 pf use 2200 pf c17 = 1/(2 p r2 f p ) = 1/(2 p x 8.2 k x 112 khz) = 173 pf use 100 pf the complete design is shown in figure 13. the pc board top and bottom views are shown in figures 17 and 18. figure 16. voltage coupling through miller capacitance
mc33470 http://onsemi.com 11 pin function description pin name description 1 g2 this is a high current dual totem pole output gate drive for the lower, or rectifier, nchannel mosfet. its output swings from ground to p vcc . during initial power application, both g2 and g1 are held low until both v cc and p vcc have reached proper levels. 2 p v cc this is a separate power source connection for driving nchannel mosfets from the g1 and g2 outputs. it may be connected to 12 v. 3 p gnd this is a separate power ground return that is connected back to the power source. it is used to reduce the effects of switching transient noise on the control circuitry. 4 a gnd this pin is the ground for the control circuitry. 5 v cc this pin is the positive supply of the control ic. 6 sense this pin is used for feedback from the output of the power supply. it has a 20 m a current source to ground which can be used to provide offset in the converter output voltage. 7 i max this pin sets the current limit threshold. 190 m a must be sourced into the pin. the external resistor is determined from the following equation: r = ([r ds(on) ] [i lim ]/[190 m a]) 8 i fb this pin has two functions. first, it provides cyclebycycle current limiting. second, if the current is excessive, this pin will reinitiate a softstart cycle. if the voltage at the i fb pin drops below the voltage at the i max pin when g1 is on, the controller will go into current limit. the current limit circuit can be disabled by floating the i max pin and shorting the i fb pin to v cc . 9 ss this is the softstart pin. a capacitor at this pin, in conjunction with a 10 m a internal current source, sets the softstart time. during moderate overload (current limit with v o > 50% of the set value), the softstart capacitor will be discharged by an internal 90 m a current source in order to reduce the duty cycle of g1. during hard current limit (current limit with v o < 50% of set value), the softstart capacitor will be discharged by a 64 ma current source. 10 comp this pin is provided for compensating the error amp for poles and zeros encountered in the power supply system, mostly the output lc filter. 11 ot this is the over temperature fault pin. ot is an open drain output that will be pulled low if the outen pin is less than 2.0 v. 12 fault this pin indicates a fault condition. fault is an open drain output that switches low if v o exceeds 115% of its set value. once triggered, the controller will remain in this state until the power supply is recycled or the outen pin is toggled. 13 p wrgd this pin is an open drain output which indicates that v o is properly regulated. a high level on p wrgd indicates that v o is within 4% of its set value for more than 400 m s. p wrgd will switch low if v o is outside 4% for more than 100 m s. 14 vid4 voltage id pin. this cmoscompatible input programs the output voltage as shown in table 2. this pin has an internal 10 k pullup resistor to v cc . 15 vid3 voltage id pin. this cmoscompatible input programs the output voltage as shown in table 2. this pin has an internal 10 k pullup resistor to v cc . 16 vid2 voltage id pin. this cmoscompatible input programs the output voltage as shown in table 2. this pin has an internal 10 k pullup resistor to v cc . 17 vid1 voltage id pin. this cmoscompatible input programs the output voltage as shown in table 2. this pin has an internal 10 k pullup resistor to v cc . 18 vid0 voltage id pin. this cmoscompatible input programs the output voltage as shown in table 2. this pin has an internal 10 k pullup resistor to v cc . 19 outen this is the on/off control pin. a cmoscompatible logic a1o allows the controller to operate. this pin can also be used as a temperature sensor to trigger the ot pin (when outen drops below 2.0 v ot pulls low). when outen drops below 1.7 v for longer than 50 m s, the controller will shut down. 20 g1 this is a high current dual totem pole output gate drive for the upper, or switching, nchannel mosfet. its output swings from ground to p vcc . during initial power application, both g2 and g1 are held low until both v cc and p vcc have reached proper levels.
mc33470 http://onsemi.com 12 table 1. voltage identification code vid4 vid3 vid2 vid1 vid0 v o 0 1 1 1 1 0 1 1 1 0 0 1 1 0 1 0 1 1 0 0 0 1 0 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 1 0 1 1.8 0 0 1 0 0 1.85 0 0 0 1 1 1.9 0 0 0 1 0 1.95 0 0 0 0 1 2.0 0 0 0 0 0 2.05 1 1 1 1 1 no cpu 1 1 1 1 0 2.1 1 1 1 0 1 2.2 1 1 1 0 0 2.3 1 1 0 1 1 2.4 1 1 0 1 0 2.5 1 1 0 0 1 2.6 1 1 0 0 0 2.7 1 0 1 1 1 2.8 1 0 1 1 0 2.9 1 0 1 0 1 3.0 1 0 1 0 0 3.1 1 0 0 1 1 3.2 1 0 0 1 0 3.3 1 0 0 0 1 3.4 1 0 0 0 0 3.5
mc33470 http://onsemi.com 13 table 2. connector pin function pin row a row b 1 5.0 v in 5.0 v in 2 5.0 v in 5.0 v in 3 5.0 v in reserved 4 12 v in 12 v in 5 reserved up# 6 i share outen 7 vid0 vid1 8 vid2 vid3 9 vid4 p wrgd 10 v ccp v ss 11 v ss v ccp 12 v ccp v ss 13 v ss v ccp 14 v ccp v ss 15 v ss v ccp 16 v ccp v ss 17 v ss v ccp 18 v ccp v ss 19 v ss v ccp 20 v ccp v ss
mc33470 http://onsemi.com 14 figure 17. pc board top view figure 18. pc board bottom view l2 l1 c1 r10 c2 r8 r9 c3 c12 c11 c10 j1 r3 r1 c5 r5 q1 q2 q3 q4 r4 r7 c6 r2 r6 r2 c16 c13 c17 d2
mc33470 http://onsemi.com 15 package dimensions dw suffix plastic package case 751d05 issue f 20 1 11 10 b 20x h 10x c l 18x a1 a seating plane h x 45 e d m 0.25 m b m 0.25 s a s b t e t b a dim min max millimeters a 2.35 2.65 a1 0.10 0.25 b 0.35 0.49 c 0.23 0.32 d 12.65 12.95 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 h 0.25 0.75 l 0.50 0.90 0 7 notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not include mold protrusion. 4. maximum mold protrusion 0.15 per side. 5. dimension b does not include dambar protrusion. allowable protrusion shall be 0.13 total in excess of b dimension at maximum material condition.
mc33470 http://onsemi.com 16 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc33470/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

▲Up To Search▲

Price & Availability of MC33470-D

	To Download MC33470-D Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .